1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, it relates to the circuit arrangement of a power semiconductor device with three terminals operable to be switched at high frequencies.
2. Description of the Prior Art
FIG. 2 shows the circuit arrangement of a conventional BIMOS switching power semiconductor device with four terminals operable to be switched at high frequencies.
Referring to FIG. 2, an n-channel MOS field effect transistor (MOS-FET) 2 is connected in parallel with an npn-type bipolar transistor 3. Namely, the drain of the n-channel MOS-FET 2 is connected with the collector of the npn-type bipolar transistor 3 and the source of the MOS-FET 2 is connected with the emitter of the bipolar transistor 3, to form a C/D terminal and an E/S terminal respectively. Between the C/D terminal and the E/S terminal, a free-wheeling diode 4 is connected in an electrically forward direction in view of the E/S terminal. To the gate of MOS-FET 2 is provided a voltage pulse from a gate driving power suuply 1, and to the base of the bipolar transistor is provided a current pulse from a base current supply 5. The operation of the MOS-FET 2 is controlled by voltage pulses from the power supply 1 for driving the gate of the MOS-FET 2 while the operation of the bipolar transistor 3 is controlled by current signals from the base current supply 5.
Refering to FIG. 2, first, a turn-on operation of the semiconductor device circuit is described. The MOS-FET 2 is turned on by the voltage pulse supplied to its gate from the gate-driving power supply 1. In synchronization with the base-driving voltage pulse from the power supply 1, the base current supply 5 supplies the base-driving current pulse to the base of the bipolar transistor 3 to turn on the same. Thus, the MOS-FET 2 and the bipolar transistor 3 perform parallel switching operations. The switching rate of the MOS-FET 2 is faster than that of the bipolar transistor 3, and hence the load current I.sub.L flowing from the C/D terminal is first bypassed by the MOS-FET 2 to flow out from the E/S terminal. When the bipolar transistor 3 is turned on and saturated, the current flowing from the C/D terminal to the E/S terminal is divided in accordance with the ratio between the collector-to-emitter saturation resistance of the bipolar transistor 3 to the drain-to-source on-resistance of the MOS-FET 2.
In order to turn off the semiconductor device, the pulses from the power supply 1 and the current supply 5 are made negative so that the MOS-FET 2 and the bipolar transistor 3 are turned off. A high-speed switching operation of the conventional semiconductor device has been performed in the aforementioned manner.
However, the aforementioned conventional semiconductor device with four terminals for parallel BIMOS switching operations has the following disadvantages: First, the conventional semiconductor device requires two driving circuits such as the power supply 1 for driving the MOS gate and the current supply 5 for driving the base of the bipolar transistor 2 as shown in FIG. 2, and the respective driving circuits must be enlarged in size as they are. The enlargement in size of the driving circuits accompanies the increased driving loss therein, and the entire system is also enlarged in size.
Further, the output current pulse from the base current supply 5 must be matched in timing with the output voltage pulse from the gate-driving power supply 1 as the condition required for the two driving supplies 1 and 5 to make the parallel operations of the MOS-FET 2 and the bipolar transistor 3. However, such matching is considerably difficult and a time lag may be caused in the timing of on/off operations of the MOS-FET 2 and the bipolar transistor 3.
Further, since the bipolar transistor 3 operates in a general switching character, i.e., in a saturation region, the storage time of the bipolar transistor 3 may attain to several .mu.sec. depending on driving conditions, causing a delay in response in the switching operation at high frequencies.
In addition, when the bipolar transistor 3 is turned off, a reverse bias is applied to its base from the base current supply 5, whereby the base current may flow in the reverse direction to exceed the limit value of the reverse bias safe operating area of the bipolar transistor 3 (particularly in case of an inductive load), thereby to damage the bipolar transistor 3. Thus, narrowed is the range of the reverse bias safe operating area of the switching semiconductor device.
Accordingly, an object of the present invention is to overcome the aforementioned disadvantages of the prior art by providing a three-terminal switching semiconductor device of BIMOS structure which can implement an inverter unit or a chopper unit safely operating preferably in a high-frequency region exceeding 100 KHz.
The circuit according to the present invention can be easily put into practice by employing components which easily come to hand and simple circuit arrangement with no employment of components hard to obtain nor complicated circuit arrangement.
Examples of the conventional semiconductor devices operable to be switched at high speed and frequencies are described in detail in "A Comparison between BIMOS Device Types" by M. S. Adler, IEEE Power Electronics Specialists Conference, June 1982, "A New BIMOS Switching Stage for 10 KW Range" by E. Heberstreit, PCI April 1983 Proceedings and "Status and Emerging Directions of MOSPOWER Technology" by Dr. Blanchard, PCI April 1983 Proceedings.